1. Field of the Invention
The present invention relates to a magnetoresistive random access memory, in particular, for example, the read circuit configuration of the magnetoresistive random access memory.
2. Description of the Related Art
Magnetoresistive random access memory (MRAM) is the nonvolatile memory that can be accessed high-speed. MRAM uses magnetoresistive effect (MR) elements to store information. A MR element takes two different resistance, corresponding to the state of magnetization. Reading is performed by distinguishing the resistance of MR elements. Therefore, the reading method of detecting the resistance of the MR element with sufficient accuracy is needed.
One of the reading methods is the differential amplification system. In the differential amplification system, the read signal current value according to the resistance state of the MR element in the memory cell for storing information is compared with reference current, and the difference of two current values is amplified. It is known that the reference signal is obtained by combing MR elements for reference cells that have different resistances to generate the mean resistance of the two resistances of MR elements for memory cells. However, this method requires more than one reference cells to generate one reference signal. For this reason, the number of the reference cells arranged in a memory cell array increases, and the share in the memory cell array of a memory cell falls.
As technology of avoiding this problem, the method of generating a reference signal by one reference cell is disclosed in the U.S. Pat. No. 6,496,436. In this method, the read bias voltage applied to a memory cell and the read bias voltage applied to a reference cell are different. And the value of the reference current that flows through a reference cell is set to the middle of the two read signal current values obtained with the two resistance values of the magnetic resistance elements for cells. Specifically, assume that the bias voltage applied to the reference cell is (Vbias1/2)+(1+Rmin/Rmax), where a bias voltage applied to the memory cell is Vbias1, the lower resistance of the memory cell is Rmin, and the higher resistance of the memory cell is Rmax. And the resistance of the reference cell is fixed to Rmax, which allows current flowing through the reference cell to be a middle of the value of current that flows through the memory cell at the low resistance state and that at high resistance state.
U.S. Pat. No. 6,496,436 discloses the circuit that generates a reference bias voltage in FIG. 3. This circuit combines an operational amplifier and dummy cells to generate the reference bias voltage. Since the reference voltage is directly applied to the reference cell, the clamp circuit that uses the negative feedback by operational amplifiers 35 and 45 as shown in FIG. 1 is needed.
This clamp circuit is required for every read circuit. And a read circuit is prepared for every memory cell block, which is an access unit of data. For this reason, it is necessary to prepare such more than one clamp circuits for a memory chip. Therefore, the cramp circuits, which are big due to operational amplifiers, occupy a large area of MRAM, resulting in smaller area available for providing memory cells.
Moreover, more than one read circuits are activated, namely, more than one clamp circuits are activated at the time of reading. For this reason, the operational amplifiers that need current flowing through them at the time of operation increase the power consumption of MRAM.